The present invention relates in general to cell-based integrated circuits such as gate arrays, and in particular, to an improved layout of basic cells to reduce the area needed for a particular design.
Gate array technology, also known as standard cell design, has been developed for quickly designing integrated circuits. Gate array technology is characterized by predesigned circuit units known as "macro cells." Macro cells are commonly used elements such as NAND gates, NOR gates, and flip-flops, etc. A designer may select a desired macro cell from a library of macro cells and place it in a design. The macro cells may be interconnected in a variety of ways to create a desired functionality for the integrated circuit. By being able to select the macro cells from a library and to place them into a design, a designer can quickly design a function without having to worry about the details of each individual transistor.
A macro cell is made up of interconnected basic cells. A basic cell is the smallest building block of the technology, and generally consists of one or more transistors. The basic cells are efficiently arranged as an array on the integrated circuit. A library of macro cells is designed from basic cells for a certain technology, and their design characteristics typically do not change from one design to the next.
Because a designer will use many macro cells in a particular design, it is important that the macro cells be designed as efficiently as possible. As described above, the macro cells are made up of interconnected basic cells. Therefore, it is important that the basic cells be designed such that they can be interconnected efficiently (local interconnections) and that the macro cells are interconnected efficiently to other macro cells and to I/O and power supply signals (global interconnections.)
One concern of a macro cell designer is to be able to route VDD and GROUND power supply traces to the transistors on the basic cells efficiently. FIG. 1 illustrates a prior art basic cell design and an integrated circuit architecture used, for example, in U.S. Pat. Nos. 5,072,285, 4,682,201, 4,884,118, 4,783,692, and others, to route power supply traces to the basic cells.
In FIG. 1, a planer representation of two basic cells 101 is illustrated. Basic cell 101 consists of two gate electrode regions 105 and 106 extending across a p-type diffusion region 110 forming a pair of PMOS transistors, and two gate electrode regions 115 and 116 extending across an n-type diffusion region 120 forming a pair of NMOS transistors. Several basic cells 101 are arranged on the substrate in rows. Power supply traces 130 and 132 are on a first level metalization layer above diffusion region 105 and extend across respective rows of the basic cells 101. Typically, power supply trace 130 serves as VDD and power supply trace 132 serves as GROUND. Most commonly, power supply traces 130 and 132 are connected to diffusion regions 110 and 120 at a common node between the two transistors.
An advantage of this architectural layout is that a direct connection can be made between power supply traces 130 and 132 and diffusion region 110 and 120 respectively, without additional metal routing. A disadvantage of this architectural layout is that power supply traces 130 and 132 block vertical connections on the first layer metalization. Routing local interconnections between nodes of a basic cell to create macro cells is necessary. With power supply traces 130 and 132 extending across the middle of each row, many vertical local interconnections are blocked on the first level of metal. This requires an increased use of a second metalization layer to allow signals to cross over power supply traces 130 in the vertical direction.
FIG. 2 represents another layout style using a modified basic cell 201 and power supply trace arrangement. It is described, for example, in U.S. Pat. No. 4,884,115, U.S. Pat. No. 5,493,135. In this layout style, basic cells 201 are arranged into rows. Modified basic cell 201 may be identical to basic cell 101 of FIG. 1, or it may be a modified design as depicted in FIG. 2. Power supply traces 211 and 212 are placed outside each row of basic cells 101. Typically, power supply trace 211 serves as VDD, and power supply trace 212 serves as GROUND. A metal connection trace 218 is placed between power supply trace 211 and p-type diffusion region 220. Typically, metal connection trace 218 is formed in the first level metalization. Similar metal traces (not shown) are used to connect power supply trace 212 with the n-type diffusion region 230.
By this arrangement, vertical routing among basic cells is not blocked on the first level metalization. However, horizontal routing is still blocked due to metal connection trace 218. In several prior art references, including U.S. Pat. No. 5,493,135, modified basic cell 201 with a diffusion extension 225 is introduced. Diffusion extension 225 reduces the necessary length of metal connection trace 218. However, some blockage of horizontal traces still occurs.
A further advantage of the style of architecture shown in FIG. 2 is depicted in FIG. 3. Adjacent rows of basic cells are inverted with respect to each other so that a single power supply trace can be shared between two rows of basic cells. For example, power supply traces 310 and 315 may serve as VDD while power supply trace 320 may serve as GROUND. By stacking inverted rows in this way, the space required for one power supply trace is saved in each row.
Even with the improvements described above, the existing architectures for design of gate arrays are still not completely efficient. As mentioned above, the architecture shown in FIG. 1 blocks vertical routing, and the architectures shown in FIGS. 2 and 3 block some horizontal routing and do not allow a direct connection between the power supply traces and the diffusion layer. A basic cell and circuit architecture that does not have these limitations is desirable.